The world we are living in today is full of complex digital systems that we need to rely on. They are becoming more sophisticated and infinite complex. The safety and security of these systems are of critical importance and the repercussions of malfunctions can be catastrophic. Even with rigorous testing, there can be numerous ways to go wrong. However, to minimize these issues, different strategies are employed by verification engineers to achieve the goal – of completeness of verification space by ensuring that a design implementation meets its specification. One of such strategies is formal verification.